Go to content

High Speed Digital

Design Services

Templetronics can offer the following expertise in high speed digital design and signal integrity to forward your designs success:

  • EMC performance
  • High device pin-out counts
  • BGA devices < 1mm pitch
  • Laminates: FR4 & polymid-aramid, Rogers
  • Power-on sequencing
  • Low power design
  • Embedded Systems

Industry standard tools
Design with leading design tools

  • Cadence Allegro HDL (inc SpectraQuest, Sigrity
  • Mentor Graphics Boardstation LMS & DX Designer
  • Mentor Graphics HyperLynx/GHz
  • Orcad
  • Altium Designer (formerly Protel DXP)
  • IBIS models + IBS AMI
  • HSPICE models
  • Zuken/Cadstar SI
  • multi-Gigabit SERDES simulation

  • Channel analysis & characterisation
  • Controlled impedance boards
  • Clock distribution
  • Crosstalk analysis & minimisation
  • Decoupling strategies and analysis
  • Differential signalling
  • High speed multi-Gbps serial interface design
  • Interconnect and channel simulation
  • Low propagation delay analysis and design
  • Low clock jitter design
  • Low PBER design
  • Low skew design
  • Low inductance design
  • Lumped and distributed system analysis
  • Microstrip and stripline transmission lines
  • Multi-layer PCB stack-up definition
  • PHYsical layer design interface: XAUI/10GbE LVDS & MII/GMII/RGMII/SGMII, PCIe & sRIO
  • Power integrity & distribution network (PI/PDN) design
  • Signal integrity (SI)
  • Signal standards interaction and interoperability
  • Single and differential data transmission
  • SSO minimization
  • SERDES and channel simulation
  • Signal integrity simulation
  • System layout and routing advice
  • Termination schemes
  • Thermal analysis
  • Time domain reflectometry (TDR)
  • Timing analysis
  • Two-port analysis and S Parameter modelling
  • Via technology (micro, blind/buried, standard PTH)

high density printed circuit board from www.freeimages.co.uk

Templetronics understands the challenges of modern high speed electronics design, and have successfully designed many complex high speed digital systems and also mixed signal systems. We have extensive experience in both signal integrity and power integrity.

Series termination on a transmission line

With serial interconnect now the norm, and data rates pushing 28GBps and 56Gbps, and moving ever higher, across backplanes, together with high bandwidth memory, we can design a robust transmission system, taking all channel elements and evaluating the components to yield successful transmission when bit widths and are shrinking to less than 10's of picoseconds narrowing unit intervals. Enhanced protocol revisions of Ethernet such as 100GbE approved and available, and 400GbE in progress and offered by some vendors already, require understanding of physical channel electrical limitations, and old and new encoding schemes to design new high bandwidth data systems and interface using legacy channels where retrofitting is preferred.

Complex packaging and PCBs pose no problem to us. We have extensive experience in board stack-up and complex device packaging including fine pitch BGA pitches.

We have extensive expertise in PCB stack-up, signal and layer allocation, parasitic via stub resonance effects, power supply distribution network and integrity design (PI/PDN), and decoupling.

We have a wealth of experience designed
multi-MegaHertz synchronous and source-synchronous interfaces, and also in multi-Gigabit serial transmission achieving low BER rates, and understanding how to achieve successful channel design.

Our experience in sub ns rise time designs will be
invaluable to your designs success.

Modern tools allow certain design rules & constraints to be input into schematics and layout stages to achieve a robust PCB through controlled design. Working closely with PCB layout partners is crucial to success, as the Layout Engineer may not necessarily understand the requirements crucial for design success.

We apply a structured methodology to circuit board design, performing static timing analysis, signal integrity checks & crosstalk analysis where necessary. We use proprietory tools to do this.

We consider the increasing power requirements required for newer devices and power delivery network performance.

See our EMC and Embedded Design Services page for more details, and also the Embedded Projects and the High Speed Digital Projects pages for more details.

Back to Top

Signal waveform on a transmission line
Eye diagram and mask

We use cookies to help maintain and improve our website.

Click the following links for our Terms of Use and Privacy and Cookie policies

The PCB image on this page is used on this website by kind permission under the terms of www.freeimages.co.uk

Home | Company | Design Services | Projects | Information | Contact | Site Map

Back to content | Back to main menu