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Digital (ASIC, FPGA, SoC)

Design Services

Templetronics is pleased to be able to provide a comprehensive ASIC and FPGA full system-on-chip design service, offering full design flow capabilities for both technology flows:

Industry standard EDA tools:

  • Mentor Graphics FPGA Designer
  • MATLAB/Simulink


  • Modelsim/QuestaSim
  • Aldec Active HDL

Synthesis and implementation

  • Cadence (Ambit/BuildGates, RTL Compiler)
  • Synopsis PrimeTime
  • Synopsis DC Compiler
  • Synplicity Synplify/Synplify Pro

FPGA vendors

  • Altera (now Intel)
  • Actel (now Microchip/MicroSemi)
  • Lattice
  • Xilinx

ASIC Technologies

  • Full ASIC flow experience
  • Standard cell, semi custom
  • 3rd party fab/P&R liason

  • HDL RTL & behavioural design
  • VHDL & Verilog languages
  • Algorithm implementations in HDL
  • Simulation & Verification: pre/post layout
  • Synthesis including incremental synthesis and PKS
  • STA (Static Timing Analysis)
  • Clock tree synthesis
  • Clock domain crossing
  • Power estimation
  • Pin-out allocation
  • Post layout verification
  • Floor planning and place and route
  • ASIC prototyping
  • FPGA design and implementation
  • VITAL timing
  • Custom algorithm design and implementation
  • SoC architecture, design and development
  • IP block design and interface & 3rd party IP integration
  • Signal integrity
  • JTAG boundary scan
  • BIST
  • Arithmetic functions in HDL
  • Low power design
  • PCB design and device integration
  • Device architecture

Templetronics offers a full ASIC and FPGA design experience from specification to sign off.

Digital ASIC Integrated Circuit

We offer full design entry to silicon service. We will not commit to silicon until full simulation and/or timing analysis has been performed on the design. We aim for a “right first time” approach for all fixed silicon devices using structured, controlled design processes from requirements to verification.

We are fully conversant in fully synchronous design. Our design strategy is to
understand the architecture of the technology we are targeting, and apply best design practices to implement the design. We have constantly achieved timing closure on designs (both ASIC and FPGA).

For ASIC design, we can offer full ASIC design flow experience, and liaise with the silicon vendor/fab. (
Note: we do not perform ASIC place and route or tape-out. These tasks are process dependent and best performed by the ASIC vendor).

From simple logic, 3rd party IP integration to complex algorithms we can code for your target technology.

We understand the segregation needed between data and control paths to get speed up. We are conversant with low ns clock designs, multiple clock domains and techniques such as pipelining and retiming, applying them where necessary.

We understand and implement complex algorithms. We will code from specification to HDL, specifically for a target technology, or utilise system design to implementation tools.

We have extensive experience in ASIC and FPGA designs covering the following genres:

  • base logic designs
  • embedded 32 bit IP processors
  • algorithm/control law/DSP implementation
  • fully custom and mixed IP design

With multiple FPGA device technology design experience from Flash to SRAM devices with the latest low power IGLOO devices from Microchip/MicroSemi (formerly Actel) to high performance SRAM devices from Xilinx (7 Series Virtex and Artix), to Intel (formerly Altera) and Lattice, we can design complex high performance programmable logic systems.

For safety critical applications we have extensive experience in robust and structured design and verification methodologies & methods (see our Expertise page).

With extensive coding and implementation crossing different vendors, both ASIC and FPGA, and a proven track record in full design flows for both ASICs and FPGAs from specification to sign-off, let us help you achieve
your designs success in digital.

As well as proven design routes such as VHDL and Verilog, we are moving towards newer integrated system design and verification /transaction modelling approaches such as SystemC/System Verilog using OVM & UVM, and on the design side, System-to-HDL design / algorithmic synthesis design flows and the UPM for low power technology.

Find out more about how
Templetronics can assist your ASIC or FPGA design.

For digital design at a PCB level please refer to our High Speed Digital and Signal Integrity and Mixed Signal design services pages.

See our Digital ASIC & FPGA Projects page for more details.

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ASIC Integrated Circuit package showing die bondwires and pins
Digital circuit netlist from synthesised HDL

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