Templetronics


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Digital (ASIC,FPGA,SoC)

Projects > Project Overviews

Here are some projects that Templetronics has successfully completed in the field of SoC design, both in ASIC and programmable logic technologies:


Application Specific Interated Circuit

ASICs & SoCs
FPGAs & Programmable Logic


Please see the Testimonials' page regarding our input.

ASICs & SOCs

Background:

Full device & design flow responsibility including: System architecture & specification; VHDL design entry (custom circuit & IP interface design); functional/pre-layout verification, synthesis, static timing analysis, gate level/post layout verification, power estimation; I/O & pin assignment

Semi-custom “sea-of gates” ASIC design targeted to 3rd party ASIC vendor processes.

Digital ASIC

The following projects have been successfully undertaken by the design expertise of Templetronics:

Digital Control ASIC, brushless DC Motor
RISC CPU SoC
Turboprop Digital Engine Control ASICs
Digital Controller ASIC, Brushed DC-motor

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Digital Control ASIC, brushless DC Motor

Project: Brushless DC-motor controller system
Description:
Highly complex digital control SoC for a brush-less DC motor system containing the above technologies & circuits. This device is the core digital processing device for a back-up electric motor/pump set to control the flight services on the A380 aircraft. The ASIC design was totalled 130k gates and the whole device, excluding one IP circuit was designed by our design expertise.

We have worked on this design twice, once with the original system concept & again when the customer wished to implement more advanced algorithms in the system. We also prototyped the ASIC in an Xilinx Virtex2 device to mitigate the risk of the design prior to sign-off.

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RISC CPU SoC

Project: Custom RISC processor SoC
Description:
Custom 32 bit RISC CPU based system with 4 stage pipeline to control an electric generator embedded system.

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Turboprop Digital Engine Control ASICs

Project: Turbo-prop digital engine controller (2 devices)
Description:
Semi-custom ASICs designed in VHDL with data acquisition, monitoring, storage, frequency to digital conversion for speed measurement of the engine, and interfaces to a CPU as part of a digital engine control system

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Digital Controller ASIC, Brushed DC-motor

Project: Brushed DC-motor controller ASIC
Description:
Highly complex digital control SoC for a brushed DC motor system containing the above technologies & circuits. This device is the core digital processing device for four electric motor driven flight surfaces. Once again the design was risk mitigated by the use of a Xilinx SRAM FPGA, this time an XC4000 series device (see below, under FPGAs ). We also designed the board and interfaces to the ASIC. See the embedded systems page for more details.

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FPGAs & Programmable Logic

This business has designed complete FPGAs in SRAM, anti-fuse and Flash technologies from vendors such as Xilinx and Actel. All FPGAs have been designed in VHDL and taken through the full FPGA design flow. Here are some of the designs we have successfully completed.

Safety Critical Industrial Algorithms
Avionics Communications Control FPGA

Avionics Video Interface
DSP FPGA
Medical DSP FPGA
CPU & Speed Measurement FPGA
Data Protocol Interface FPGA
Digital Motor Control FPGA




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Safety Critical Industrial Algorithms

Project: Safety Critical Power Controller and Data Acquisition
Description
Our design expertise has designed complete complex algorithms targeted to SRAM FPGAs, targeted to Xilinx Spartan6 devices. These functions provided BIT (Built In Test) functions for safety critical control functions, exercising hardware during specific equipment operational phases to determine the availability and integrity of the plant equipment by analysing plant feedback and reporting to an overriding controller. Interface to plant was to AC control electronics.

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Avionics Communications Control FPGA

Project: Avionics Communications and Flight Monitoring System
Description
Targeting a low power ProASIC3 device, a signal conditioning system with FPGA control was designed in VHDL to communicate with a master system using ARINC 429 protocol to avionics DO 254 standards.

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Avionics Video Interface
Project: Avionics Flight Display System
Description
Targeting a low power ProASIC3e device, an 18bit RGB interface was designed VHDL to communicate with a master processor and drive an LCD TFT display to avionics DO 254 standards.

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DSP FPGA

Project: Digital multi-decimation and sync filter
Description
Targeting a Virtex5 series device, using processing internal clocks speeds of above several hundred MHz, this complex design was implemented in VHDL and implemented with full datapath and control segregation in mind to achieve timing closure using pipelining techniques to achieve sub-5ns performance, and high-performance on-chip design resources for fast data throughput to/from peripherals such as QDR2 memory.

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Medical DSP FPGA

Project: Detection and processor for medical applications
Description
Targeting a Xilinx Artix 7 series device, using processing internal clocks speeds of 40MHz and 200MHz, and utilising on board SRAM memory for data storage, this very interesting design was implemented in VHDL and implemented with full datapath and control segregation (hence the separate clock domains) in mind to achieve timing closure using structured techniques to achieve 5ns (or higher) performance.

Our system design knowledge created an algorithmic model in MATLAB/Simulink, of the full electronic system, from primary sensor signal conditioning to digital algorithms, enabling us to prove the implementation concept and digital filtering strategy prior to design implementation using model driven design, and performance. A standard technique we have used across multiple algorithmic designs, both control system and DSP based designs.

This system was another example of embedded co-processing using an FPGA, a very flexible device, as a workhorse in computation, whilst offloading the result to a host CPU. In contrast to most FPGA designs the I/O utilisation on this was greatly reduced, due to the system interfaces, with the device resource being driven by on board storage requirements, providing sufficient bandwidth due to the die characteristics. With plenty of logic resource due to the larger memory requirements, internal design was not an issue.

Using a high sampling rate with a pipelined ADC, specifically designed for the software defined radio (SDR) market, this data acquisition and processing engine provided a workhorse design for the entire system, with the downstream CPU only used as a system manager.

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CPU & Speed Measurement FPGA

Project: Embedded power controller system (x 2 devices)
Description:
Antifuse FPGA design for interfacing to an Intel 80C186 CPU and also speed measurement. The FPGAs were designed to perform address decoding and control on a data acquisition card, and also to create a digital representation of speed from a raw frequency input from an inductive pick-up sensor. We met stringent timing targets within the system with regard to the processor write cycle. We also provided consultation to the customer over board level issues, and provided a repeatable design flow from design to implementation for use with OTP FPGAs, de-risking the use of these devices. We also performed all the engineering activities in time to prevent the customer from forfeiting a multi million euro late delivery penalty!

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Data Protocol Interface FPGA

Project: Embedded generator control FPGA system
Description:
This system was based around a 32 bit RISC CPU IC. The FPGA was a custom VHDL design with a CAN interface and also an serial interface based around the Philips IC protocol. We picked up parts of the design, re-writing the VHDL, and getting the gate-count down to enable a cheaper device to be used, thereby reducing system costs. We also designed a complex arbitration scheme between the two systems to enable a RAM to be used for temporary data storage. We also provided consultation to the customer over board level, VHDL and analogue design issues.

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Digital Control FPGA

Project: Brushless DC-motor controller FPGA
Description:
This was an ASIC prototype of the above ASIC. It was created for rapid prototype for system/board level tests and ASIC risk mitigation to prove some complex algorithms for the control system.

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Digital Motor Control FPGA

Project: Brushed DC-motor controller FPGA

Description:
This was an ASIC prototype of the above ASIC. It was created for rapid prototype for system/board level tests and ASIC risk mitigation. Incidentally we also designed the board and associated circuits around the IC. As well as the features of the ASIC, it had a dual clock domains.

For more details , see the DSP Projects page, Embedded Systems project page, the Digital ASIC & FPGA, the EMC & High Speed Digital/SI projects pages and Mixed Signal projects page for more information.


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